The present invention is directed to a circuit for minimizing the number of external pins or terminals on a memory device. More particularly, the present invention is directed to a memory device wherein the external power and ground pin functions are merged with other pin or terminal functions.
Pin reduction for purposes of increasing the number of memory devices that can be assembled in a given area allocated to computer memory is the subject of co-pending U.S. application Ser. No. 812,290 filed July 1, 1977, entitled "A Minimum Pin Memory Device", and co-pending U.S. application Ser. No. 895,328 filed Apr. 11, 1978, entitled "Memory Device Having A Reduced Number of Pins", which applications are both assigned to the same assignee as the present application.
In the aforementioned application Ser. No. 812,290, pin reduction is accomplished by merging the functions provided by signals on various pins. A first terminal provides both a clocking and a memory select function. A second terminal is bi-directional and provides memory mode selection, address and data input and output functions.
Further pin reduction is provided for in the second of the abovementioned applications, namely U.S. application Ser. No. 895,328. In such application, a circuit is provided in a memory device for receiving signals applied to two external pins. A threshold detector in the circuit detects the difference in voltage level of the signals; when such difference reaches a predetermined level, the signals are applied to the power and ground terminals of an internal power supply within the memory device. Thus, the need for external power and ground terminals in a memory device is eliminated.
The subject matter of the present application provides an alternative approach to further pin reduction and the elimination of external power and ground terminals in a memory device.